1. Field of the Invention
This invention relates to integrated circuit testing devices, and more particularly to the use of a FIFO memory to promote uniform communication of test data from a dynamic random access memory (DRAM) to a device under test.
2. Description of the Related Art
As large scale integrated circuit (LSI) components become more complex, the need for larger local memory in LSI component testers increases accordingly. For example, state of the art LSI component testers must have the capability of storing up to eight million or more vectors in local memory. The increase is caused by the ever increasing length of test patterns for complex devices, especially those which are CAD generated. Because of such memory requirements, it is desirable to use dynamic random access memories (DRAM's) as the components used in building the local memories because they provide the largest amount of storage per dollar.
One obstacle which must be overcome when using DRAM's for test data is that they need to be refreshed periodically, and this requirement interferes with the need for a continuous data stream by the testing unit. In the past, this problem has been overcome by using two buffers between local memory and the test station. One buffer is loaded from local memory, while the other one is emptied out. By the time the second buffer is empty, the first has been filled. Thereafter, the first buffer is emptied while the second buffer is being filled. See U.S. Pat. No. 4,451,918 issued to Gillette. However, this solution requires a substantial amount of duplication of circuitry and complex control circuitry.
Another obstacle which must be overcome when using DRAMS for test data is that a DRAM running in one of the fast access modes (e.g., static column mode, page mode. nibble mode, etc.) can do only a limited number of fast accesses before it must revert to a normal, slower write or read cycle. For example, when a 256k .times. 4 DRAM is accessed in static column mode, a longer access time results every time a new row is addressed, i.e., after 512 cycles (row .times. column = 512 .times. 512 =256k). While the static column mode cycles can be 60 ns, the longer cycle which occurs when crossing a row boundary is at least twice as long. This amounts to a break in the smooth data stream.